1. Field of the Invention
Generally, the present disclosure relates to the field of fabricating integrated circuits, and, more particularly, to the monitoring of process flow quality and production yield by evaluating measurement data.
2. Description of the Related Art
Today's global market forces manufacturers of mass products to offer high quality products at a low price. It is thus important to improve yield and process efficiency to minimize production costs. This holds especially true in the field of semiconductor fabrication, since, here, it is essential to combine cutting-edge technology with mass production techniques. It is, therefore, the goal of semiconductor manufacturers to reduce the consumption of raw materials and consumables while at the same time improve process tool utilization. The latter aspect is especially important since, in modern semiconductor facilities, equipment is required which is extremely cost-intensive and represents the dominant part of the total production costs. Consequently, high tool utilization in combination with a high product yield, i.e., with a high ratio of good devices to faulty devices, results in increased profitability.
Integrated circuits are typically manufactured in automated or semi-automated facilities, thereby passing through a large number of process and metrology steps to complete the devices. The number and the type of process steps and metrology steps a semiconductor device has to go through depends on the specifics of the semiconductor device to be fabricated. A usual process flow for an integrated circuit may include a plurality of photolithography steps to image a circuit pattern for a specific device layer into a resist layer, which is subsequently patterned to form a resist mask used in further processes for forming device features in the device layer under consideration by, for example, etch, implantation, deposition, polish and anneal processes and the like. Thus, layer after layer, a plurality of process steps are performed based on a specific lithographic mask set for the various layers of the specified device. For instance, a sophisticated CPU requires several hundred process steps, each of which has to be carried out within specified process margins so as to fulfill the specifications for the device under consideration. Since many of these processes are very critical, a plurality of metrology steps have to be performed to efficiently monitor and control the process flow. Typical metrology processes may include the measurement of layer thickness, the determination of dimensions of critical features, such as the gate length of transistors, the measurement of dopant profiles, the number, the size and the type of defects, electrical characteristics, such as the transistor drive current, the threshold voltage thereof, i.e., the voltage at which a conductive channel forms in the channel region of a field effect transistor, the transconductance, i.e., the change of drive current with gate voltage, and the like. As the majority of the process margins are device-specific, many of the metrology processes and the actual manufacturing processes are specifically designed for the device under consideration and require specific parameter settings at the adequate metrology and process tools.
In a semiconductor facility, a plurality of different product types are usually manufactured at the same time, such as memory chips of different design and storage capacity, CPUs of different design and operating speed and the like, wherein the number of different product types may even reach one hundred and more in production lines for manufacturing ASICs (application specific ICs). Since each of the different product types may require a specific process flow, different mask sets for the lithography, specific settings in the various process tools, such as deposition tools, etch tools, implantation tools, chemical mechanical polishing (CMP) tools, metrology tools and the like, may be necessary. Consequently, a plurality of different tool parameter settings and product types may be encountered simultaneously in a manufacturing environment, thereby also creating a huge amount of measurement data, since the measurement data are typically categorized in accordance with the product types, process flow specifics and the like.
Hereinafter, the parameter setting for a specific process in a specified process tool or metrology or inspection tool may commonly be referred to as process recipe or simply as recipe. Thus, a large number of different process recipes, even for the same type of process tools, may be required, which have to be applied to the process tools at the time the corresponding product types are to be processed in the respective tools. However, the sequence of process recipes performed in process and metrology tools or in functionally combined equipment groups, as well as the recipes themselves, may have to be frequently altered due to fast product changes and highly variable processes involved.
Consequently, since typically several hundred process steps may be involved for forming sophisticated integrated circuits, such as CPUs, memory devices and the like, a complex sequence of manufacturing steps may be involved for each product type, wherein the finally obtained quality of the completed semiconductor product may, therefore, depend on a large number of process parameters, each of which may be subjected to a certain degree of variability due to recipe changes, process tool variations and the like. Due to the many process steps involved, which may typically require several weeks for completing the product type under consideration, it is extremely difficult to respond to customer demand within a time span that is shorter compared to the overall process time including the measurement of the final quality distribution of the product type under consideration. For example, if products of enhanced quality grade, such as microprocessors of a higher speed grade, including cache memories of increased storage capacity and the like, may be required by the customer, it may be difficult to predict whether or not a sufficient amount of products may be available on the basis of the currently being processed products, since it is difficult to assess the influence of a recipe change and the like on the final quality distribution of the products. Similarly, any disturbance of the manufacturing environment, which may be caused by subtle variations of equipment, an inappropriate setting of target values for individual process modules and the like, may remain unobserved in increased time periods, that is, until a finally obtained quality distribution may enable an estimation of the status of the manufacturing environment at the time the respective products have been produced. For example, if a measured quality distribution may indicate a sufficient amount of high quality products, while in the meantime a disturbance has occurred, a significantly reduced product quality may be produced over the next several weeks, which may result in the production of a high number of wrong products. With reference to FIGS. 1a-1b, a typical manufacturing environment for producing semiconductor products will now be described so as to discuss further problems related to the efficient estimation of the product quality during the manufacturing of semiconductor devices.
FIG. 1a schematically illustrates a manufacturing environment 150 which is to represent a facility configured to produce semiconductor products at least to a certain stage of completeness, for instance to a stage in which fully functional semiconductor devices are provided on substrates while, for instance, additional fabrication processes, such as the separation into individual semiconductor chips, the packaging thereof and the like, may be performed in other manufacturing environments. The environment 150 comprises a plurality of process tools and metrology tools, which may frequently be grouped into functional modules in which certain types of related process steps may be performed. For example, the environment 150 may comprise a plurality of process modules 160A, 160B, 160C, wherein each module may comprise a plurality of process tools and metrology tools as required for performing a plurality of related manufacturing processes. For instance, the process module 160A may represent a plurality of process tools and metrology tools which may be used for performing sophisticated lithography processes in combination with corresponding pre-exposure and post-exposure processes, development of resist material and the like. In other process modules, complex etch processes may be performed on the basis of appropriate process tools, possibly in combination with respective cleaning processes and the like, as may be required by the overall process strategy. In other cases, deposition tools may provide the capability of depositing and forming material layers with a high degree of controllability on the basis of thermally activated deposition techniques, such as low pressure chemical vapor deposition (CVD), oxidation and the like. In other process modules, implantation tools may be provided which may typically be used for incorporating any desired species, such as dopant species for modifying the conductivity of semiconductor regions and the like. Consequently, the modules 160B, 160C may represent a plurality of appropriate process tools for performing at least one manufacturing process in accordance with a predefined process recipe, wherein the recipe may change in the same process tool depending on the product type to be processed, as previously explained. It should be appreciated that dividing the manufacturing environment 150 into respective process modules may be arbitrary and may depend on the overall configuration of the manufacturing environment under consideration. Furthermore, it should be appreciated that typically a plurality of the manufacturing processes may be associated with appropriately designed metrology processes so as to monitor and control the results of the previously performed processes. Furthermore, the manufacturing environment 150 may comprise an “interface” 190 that is typically provided in the form of an automated or semi-automated transport system which interconnects the various process modules 160A, 160B, 160C in order to supply substrates to be processed and to receive substrates that have been processed in the corresponding process tools or metrology tools. For this purpose, the process modules 160A, 160B, 160C and the transport system 190 may be operated such that a desired high overall throughput of the manufacturing environment 150 may be accomplished by supplying the various product types according to their current manufacturing stage to the process modules 160A, 160B, 160C, as is required for the next step in the overall manufacturing flow. For example, on the right-hand side of FIG. 1a, a typical process flow for forming sophisticated semiconductor devices on the basis of CMOS technology is illustrated, wherein the various process stages shown may be reached by being processed in the one or more process modules 160A, 160B, 160C at least once, while typically the products may be passed through the various process modules several times, wherein the corresponding process recipes may be adapted to the desired process results to be obtained in the corresponding manufacturing stage.
For example, substrates 151 may have formed thereon a plurality of die regions 152, each of which may represent a semiconductor device including a very large number of individual circuit elements, such as transistors, capacitors, resistors and the like, as is required for the desired functional behavior of the semiconductor product under consideration. For convenience, the die regions 152 may also be referred to as semiconductor devices. As an example of a circuit element, a field effect transistor 153 may be referred to in order to demonstrate a typical overall manufacturing process. In the manufacturing stage shown, the field effect transistor 153 may comprise a gate electrode 153A, which is formed above a semiconductor region 153B and separated therefrom by a gate insulation layer 153C. As is well-known, the operational behavior of the transistor 153 may be substantially determined by the characteristics of the gate electrode 153A and the gate insulation layer 153C, as also explained above. That is, the length of the gate electrode 153A, i.e., in FIG. 1a the horizontal extension of the gate electrode 153A, in combination with the material composition and the thickness of the gate insulation layer 153C may have a significant influence on the overall controllability of a conductive channel that forms in the semiconductor region 153B at the gate insulation layer 153C upon application of an appropriate control voltage to the gate electrode 153A. Similarly, a vertical dopant profile in the semiconductor region 153B that may have previously been established prior to the formation of the gate electrode 153A may also have a significant influence on electrical characteristics of the transistor 153, for instance with respect to threshold voltage, current drive capability and the like. Consequently, since the operational behavior of the individual transistors 153 may have a significant influence on the final operational behavior of the semiconductor device 152, for instance with respect to overall speed, precise control of the manufacturing techniques for forming the gate electrodes 153A, the gate insulation layer 153C and the like may be required. For example, respective processes for forming the gate electrode 153A may be accomplished on the basis of manufacturing processes formed in at least some of the process modules 160A, 160B, 160C. For example, forming the transistor 153 as shown in this early manufacturing stage, indicated as stage I, may include sophisticated lithography techniques for forming trenches for isolation structures (not shown) and subsequently depositing appropriate materials, such as silicon dioxide, silicon nitride and the like, in accordance with specified deposition recipes. Thereafter, excess material may be removed, for instance by CMP, and thereafter a dielectric material may be formed, for instance by deposition and/or oxidation, in accordance with the requirements for forming the gate insulation layer 153C. Next, the gate electrode material may be deposited and thereafter a further sophisticated lithography process may be performed to provide an appropriate etch mask for patterning the gate electrode 153A and the gate insulation layer 153C.
In a later manufacturing stage II, the transistor 153 may, for instance, comprise a sidewall spacer structure 153D, which may be used for defining an appropriate vertical and lateral dopant profile for drain and source regions 153E. Since the spacer structure 153D at various intermediate manufacturing stages may be used as an implantation mask for defining the profile of the regions 153E, the dimensions of the spacers 153E, in combination with the implantation processes, may also have a significant influence on the overall electrical characteristics of the transistor 153. For example, respective manufacturing processes involved in forming the transistor 153 as shown in the manufacturing stage II may involve the deposition of appropriate spacer materials, such as silicon nitride, possibly in combination with etch stop materials such as silicon dioxide and the like, which may subsequently be etched in order to obtain the spacer structure 153D with a width as required for profiling the regions 153E. Thereafter, an implantation process may be performed to introduce the dopant species on the basis of appropriate implantation parameters, such as implantation energy and dose, followed by anneal processes for activating the dopants and curing implantation-induced damage.
It should be appreciated that, prior to and after the manufacturing stage II, or prior to and after the manufacturing stage I, various manufacturing processes may also have to be performed in accordance with the overall process strategy to obtain the desired transistor performance. For instance, for transistors in the deep sub-micron range, control of short channel effects may require extremely thin insulation layers which may have a thickness of 1-2 nm for silicon dioxide-based materials, which in turn may result in increased leakage currents through the gate dielectric material. Hence, further device scaling may require the incorporation of high-k dielectric materials and/or appropriate adaptation of the overall dopant profiles in the channel region of the transistor 153 to obtain an acceptable threshold voltage and maintain channel controllability, which, however, may result in a reduction of the channel conductivity. Thus, frequently, intentional strain may be created in the channel regions of the transistors in order to enhance the electron mobility to provide enhanced transistor performance for scaling the device dimensions, while the thickness of the gate dielectric material may be maintained at a thickness considered acceptable in view of leakage currents. Thus, a plurality of strain-inducing mechanisms may be employed wherein, for instance, for P-channel transistors, frequently an appropriate semiconductor alloy may be incorporated, for instance in and/or adjacent to the channel region, in order to obtain a desired type of strain. Hence, also in this case, additional complex manufacturing techniques may be required, the process results of which may also have a significant influence on the finally obtained electrical characteristics of the transistor 153.
In stage III, the semiconductor device 152 is illustrated in a further advanced manufacturing stage in which a contact structure 154 and a metallization system 155 may be provided. For example, the contact structure 154 may include an interlayer dielectric material, such as silicon dioxide and the like, in order to enclose the transistors 153, wherein respective contact elements may connect to contact areas of the transistors 153, such as the drain and source regions 153E and the gate electrode 153A. The metallization system 155 may comprise a plurality of metallization layers, wherein, for convenience, a first metallization layer 155A and a subsequent metallization layer 155B are illustrated. In the metallization layers 155A, 155B, respective metal lines and vias are provided to establish the overall required connection of the circuit elements, such as the transistors 153, in accordance with the overall circuit layout. It should be appreciated that the characteristics of the contact structure 154 and the metallization system 155 may also have a significant influence on the overall electrical performance of the semiconductor device 152. For example, in sophisticated semiconductor devices having critical dimensions of 0.1 μm, for instance with respect to the gate length, the signal propagation delay in the metallization level 155 may also play an important role and may even be more critical than corresponding signal propagation delay in the device level. Consequently, complex manufacturing strategies have been developed, for instance by replacing aluminum with copper or copper alloys and also using low-k dielectric materials in order to reduce the parasitic RC time constants in the metallization system 155. The handling of copper in the environment 150, as well as the use of low-k dielectric materials, which typically have reduced mechanical stability compared to conventional dielectrics, such as silicon dioxide, silicon nitride and the like, may require advanced manufacturing strategies which may also have a significant influence on the overall electrical performance. For example, in addition to requiring a specified electrical behavior, the metallization system 155 may also have to exhibit a certain performance with respect to electromigration in order to guarantee a specific device performance over a specified lifetime. The electromigration behavior of metal features in the metallization system 155 may significantly depend on the materials used, such as conductive and dielectric barrier materials, dielectric interlayer materials and the like, as well as the fabrication processes used, which may thus require a thorough monitoring of the processes involved in the fabrication of the metallization system 155.
FIG. 1b schematically illustrates the environment 150 when processing substrates 151 according to one or more specified manufacturing flows for respective product types. For example, it may be assumed that the substrates 151, which may typically be handled in the environment 150 in certain groups or lots, may represent a specific product type, such as a CPU, a memory device and the like, which may thus be processed in the environment 150 by passing the substrates 151 one or several times through the process modules 160A, 160B, 160C, as previously explained. The entire sequence of process steps may be referred to as a manufacturing flow 170, which may comprise a plurality of sequences 170A, 170B, 170C which, for instance, may be performed in the corresponding modules 160A, 160B, 160C according to appropriate process recipes corresponding to the respective manufacturing stage, as previously explained. Typically, respective manufacturing processes 171 may be associated with a corresponding metrology process 172, at least in many of the sequences 170A, 170B, 170C, in order to monitor and control the overall process quality. For example, in the sequence 170A, the metrology process 172 may provide measurement data which may be used for controlling the associated manufacturing process or processes 171, for instance by providing a corresponding feedback control loop. For example, upon measuring the line width of resist features after exposing and developing a resist material for forming an etch mask for patterning the gate electrodes 153A, the exposure dose of the lithography process may be adjusted for subsequent substrates to be processed, thereby providing an efficient feedback control mechanism. However, since a plurality of further manufacturing processes may be involved for forming a corresponding resist mask, such as pre-exposure baking, post-exposure baking, spin-coating of the resist material, accuracy of the alignment process and the like, and due to the fact that the measuring of the process output may be performed on the basis of selected samples in view of overall throughput of the environment 150, a certain degree of variability of the process output may nevertheless occur.
Furthermore, due to the restricted amount of measurement data, since not all die regions of each substrate can be measured for economical reasons, typically predictive control algorithms may be used, in particular when a certain degree of delay is involved in obtaining the measurement data, in which the process results may be calculated on the basis of measurement data and the tool settings may be predicted for a currently being processed product so as to obtain the desired outcome. Furthermore, respective measurement results obtained in one sequence 170A may also be used in other processes still to be performed, thereby providing a respective feed forward control mechanism. Typically, the overall process flow 170 may be controlled on the basis of a supervised control system, such as an MES (manufacturing execution system) 180, which is responsible for the appropriate material supply and initialization of the appropriate process recipe at the various process tools. Thus, after completing the manufacturing flow 170, which may include several hundred individual process steps, the substrate 151 may have formed thereon the semiconductor devices 152, wherein, however, across the various substrates 151 and also within each individual substrate 151, a variation of the finally obtained electrical characteristic of the devices 152 may be observed. For this reason, a final electrical test for obtaining representative electrical characteristics of the devices 152 may be performed for each of the devices 152 of each substrate 151 leaving the environment 150, which is typically referred to as electrical wafer sort process, wherein the corresponding electrical characteristics, such as operating speed in the form of a ring oscillator frequency, current drive capability, overall power consumption, access time for memory cells, the amount of available storage in storage devices or CPU cache areas, threshold voltage of transistors and the like, may be determined, which is a time-consuming process.
Furthermore, the respective electrical characteristics may be used to determine a yield or quality distribution for the devices 152 for the plurality of substrates 151, for instance with respect to certain quality specifications, such as speed grade and the like. Consequently, in view of economic reasons, the environment 150 should provide a high throughput with a quality distribution in accordance with specific customer demands. Although the environment 150 may include a plurality of efficient control mechanisms in the form of metrology processes and respective control strategies, such as APC (advanced process control) strategies, the environment 150 may represent a complex organism in which even subtle changes in some parts of the “organism” may result in a significantly different final quality distribution of the electrical characteristics, which may finally define the overall functional behavior of the semiconductor devices under consideration. For example, due to the complexity of the manufacturing flow 170, a non-desired quality distribution may be obtained, even though the individual sequences 170A, 170B, 170C may be within the predefined process margins. For example, it is very difficult to assess the influence of the various manufacturing processes due to the complex mutual interaction on the finally obtained quality distribution. If, for example, a different quality distribution may be required on short notice due to customer demand, it may be difficult to assess whether or not the respective quality distribution may be achieved on the basis of the currently being processed substrates, or it may be very difficult to decide how to change the process targets for the various sequences in view of the new desired quality distribution. Thus, great efforts are made in predicting the finally obtained quality distribution on the basis of measurement results, which may conventionally be accomplished by estimating the electrical parameters of the completed product by using a small number of measurement results, for which correlations with the finished product are known. However, due to the high complexity, as previously explained, the large number of unknown influences may nevertheless result in a high degree of inaccuracy of the respective yield predictions so that, for instance, in view of change of quality specifications, typically products may be measured before a corresponding prediction model may be generated.
The present disclosure is directed to various methods and systems that may avoid, or at least reduce, the effects of one or more of the problems identified above.